Apparatus and method for reducing interposer compression during molding process

ABSTRACT

A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.

FIELD OF THE INVENTION

[0001] The invention generally relates to the packaging of semiconductorchips, and more particularly to inhibiting damage to semiconductor chippackaging structures during package molding.

BACKGROUND

[0002] The fabrication of packaged semiconductor chips or dies is wellknown. One conventional ball grid array (BGA) packaging method includesaffixing a fabricated die to a substrate and electrically connecting thedie to conductive leads on the substrate. The electrical connection maybe through wire bonding or other known connection techniques whichcouples bond pads on the die to corresponding leads on the substrate. Aplastic molding material is then typically applied to the die andsubstrate for encapsulating the die on the substrate. Exposed contactson the substrate connected to the conductive leads are used toelectrically connect the packaged die to a circuit board. The moldingmaterial is typically applied by placing the die and substrate in a moldand injecting molding material over the die and substrate and exerting aforce by way of a mold clamping mechanism.

[0003] A recurrent problem associated with the molding process is thatthe force applied to the substrate during molding is often greater thanthe ability of the substrate to resist compression, and thus the forceexerted on the die and substrate often damages the delicate wiringand/or the contacts on the substrate, thereby destroying the viabilityof the packaged product. Further, the compressive forces encounteredduring molding may cause distortion of the substrate which in turncauses the plastic encapsulation material to leak onto undesired areasof the substrate, producing a defective package for the die.

[0004] A conventionally fabricated BGA semiconductor die package 10 isshown in FIGS. 1-3. The package 10 includes a die carrier 12 whichincludes an interposer layer or substrate 14 and a first solder masklayer 16, which isolates areas of the substrate 14 that are to be bondedto a die 18 supported by the carrier 12. The substrate 14 has a trench25 (FIGS. 2-3) to allow conductive leads 34 formed on the substrate 14to interconnect with bond pads 47 on the die 18. These conductive leads34 are connected with conductive traces on the substrate 14, which inturn connect with external contacts 28. The die 18 is positioned on asurface of the first solder resist layer 16 and has bond pads 47 whichconnect with respective conductive leads 34 through conductively linedholes 45 provided in the solder mask 16. The die carrier 12 is dicedfrom a carrier strip, which may include up to twelve separable diecarriers. Alternatively, the die carrier may be diced from a carriermatrix, which may include numerous rows and columns of separable diecarriers.

[0005] Most substrates 14 are formed of either a glass weave reinforcedresin or a tape. A second solder mask 20 is provided on a surface 15 ofthe substrate 14, leaving exposed the contacts 28 and shielding theconductive leads 34 running along the surface 15 from the contacts 28 tothe centrally-located trench 25. Specifically, located on a surface 15of the substrate 14 and exposed by openings within the second soldermask layer 20 are the plurality of contacts 28 which will have solderballs screen printed thereon for use in connecting the die package 10,after package molding, to a printed circuit board. Wiring in the form ofthe conductive leads 34 is shown extending into the trench 25 tocontacts 45 provided in holes in the first solder mask layer 16 to bondpads 47 of the die 18. Some of the contacts 28 may be formed asopenings, such as openings 30 extending through the substrate 14. Aftermolding, a mold material strip 24 fills the trench 25 on one side of thesubstrate 14 and provides protection to the wiring 34 extending into thetrench 25 to the die 18. The mold material 24 also covers the die 18 andextends slightly outwardly thereof onto the substrate 14. The moldmaterial 24 is only partly shown in FIG. 2 for clarity of illustration.

[0006] When a mold material, such as the mold material 24 (FIGS. 1-3),is applied to the die 18, the substrate 14, and both solder resistlayers 16, 20 by injection into a mold cavity, a force is exerted on thesurface 19 of the die 18. This causes a compressive force to be exerteddown on the substrate 14 squeezing together its opposite surfaces. Thesecompressive forces may destroy the wiring 34 on each surface of thesubstrate 14, rendering the packaged product useless. Further, thesecompressive forces may also cause the mold material strip 24 to weepover the solder mask 20, creating an undesirable mold material mass 26(FIG. 1) which may cover one or more of the contacts 28, again renderingthe packaged product useless.

SUMMARY

[0007] In one aspect, the invention provides a semiconductor die carrierwhich includes a substrate which has greater resistance to compressiveforces. The substrate includes holes extending therethrough which arefilled with a material which has a greater resistance to compressiveforces than the substrate itself, thereby reducing the possibility of adefective product being produced by compression of the substrate duringpackage molding.

[0008] In another aspect, the invention further provides a method offabricating a semiconductor die package. The method includes forming asubstrate having a plurality of holes extending therethrough, fillingthe plurality of holes with a material which has a greater resistance tocompressive forces than the substrate, attaching a die to the substrate,and encapsulating the die and a portion of the substrate with a moldmaterial.

[0009] These and other advantages and features of the invention will bemore readily understood from the following detailed description of theinvention which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a top view of a conventionally fabricated semiconductordie package.

[0011]FIG. 2 is a cross-sectional view taken along line II-II of thesemiconductor die package of FIG. 1.

[0012]FIG. 3 is a close-up view taken within circle III of thesemiconductor die package FIG. 2.

[0013]FIG. 4 is a top view of a semiconductor die package constructed inaccordance with an embodiment of the invention.

[0014]FIG. 5 is a cross-sectional view taken along line V-V of thesemiconductor die package of FIG. 4.

[0015]FIG. 6 is a close-up view taken within circle VI of thesemiconductor die package of FIG. 5.

[0016]FIG. 7 illustrates a processor-based system constructed inaccordance with an embodiment of the invention.

[0017]FIG. 8 is a flow diagram of a method for fabricating asemiconductor chip in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0018] FIGS. 4-6 illustrate a semiconductor package 100 fabricated inaccordance with an embodiment of the invention. The package 100 has adie carrier 12 which includes an interposer layer or substrate 14 havingwiring traces on a surface thereof, and a first solder mask layer 16which covers the wiring traces. The die carrier 12 may be diced from acarrier strip, which may include up to twelve separable die carriers, oralternatively, the die carrier may be diced from a carrier matrix, whichmay include numerous rows and columns of separable die carriers. A die18 is attached to a surface of the solder mask layer 16, preferably withan adhesive (FIG. 5). The substrate 14 typically comprises a glass weaveimpregnated with a resin, such as BT resin, although any suitable diesupport material, such as, for example, a tape may be used.

[0019] A second solder mask layer 20 is positioned on a surface 15 ofthe substrate 14, leaving the contacts 28 exposed. The solder mask layer20 covers conductive leads or wiring 34 on the upper surface 15 exceptwhere the contacts 28 are located. The wiring 34 on the upper surface 15of the interposer layer 14 extends into a trench 25 where connectionsare made to bond pads 47 on the die 18 through connectors 45. At leastone, and preferably a plurality, of supports 28′ extend through thesolder mask layer 20 and the substrate 14. Each support 28′ includes avia 30 which may comprise a conductive material of, e.g. copper, thoughany conductor can be used. Also, the via 30 does not have to include aconductor therein.

[0020] To inhibit damage to the substrate 14, solder masks 16, 20, thewiring 34, and the contacts 28 and/or to inhibit weeping of moldingmaterial onto contacts 28 caused by compression, a material 32 having ahigher resistance to compression than the material of the substrate 14is placed within selected vias 30. In lieu of, or in addition to,placing the compression resistant material 32 within the vias 30, slots29 formed within and extending through the substrate 14 and/or soldermask 20 may include the compression resistant material 32. Asillustrated in FIG. 4, the slots 29 are L-shaped, although slots oropenings of any suitable shape may be utilized.

[0021] The compression resistant material 32 has as a definingcharacteristic a greater resistance to compression than at least thematerial of the substrate 14 and preferably the solder resist layers 16and 20 as well, and more preferably, a resistance which will withstandthe clamping force exerted during the molding process. The compressionresistant material 32 may also have a lower moisture absorptioncoefficient, a higher glassy temperature (T_(g)) and a lower coefficientof thermal expansion (CTE) than the material of the substrate 14 and thesolder resist layers 16 and 20. The higher glassy temperature T_(g) is alimited temperature range at which a material changes from aflexible/pliable state to a solid. In this temperature range, thematerial's CTE also changes.

[0022] Preferably, an epoxy including filler particles is used for thecompression resistant material 32. One suitable epoxy, manufactured bySumitomo, is commercially available as PHP-900. Four separate versionsof the PHP-900 material are suitable as the compression resistantmaterial 32. The versions IR-1 and IR-6 are thermal cure epoxies. Theversions DC3 and DC5-4 are ultraviolet and thermal cure epoxies. Othersuitable materials for the plug material 32 include HBI-2000,manufactured by Taiyo, and Hitachi Chemical's MCF6000E. Suitable fillerparticles include silica.

[0023] The compression resistant material 32 should fill the interiorspace of the vias 30 and/or slots 29 to such an extent that substratedamage and mold material leakage due to mold compression is mitigated.The compression resistant material 32 may entirely fill or onlypartially fill the vias 30 and/or the slots 29.

[0024] With specific reference to FIG. 8, next will be described oneexemplary processing sequence for fabricating the semiconductor diepackage 100. At step 200, the die carrier 12 is fabricated, includingpreparation of the contacts 28, supports 28′, slots 29 (if used), andvias 30. The supports 28′ and the optional slots 29 also include thecompression resistant material 32 which inhibits compression of thesubstrate 14. At step 210, the die 18 is attached to the die carrier 12.The die 18 is preferably attached to the chip carrier 12 with anadhesive. At step 220, the adhesive attaching the die 18 to the carrier12 and the die 18 is cured. At step 230, the wiring 34 is attachedbetween the contacts 28 and 30, if used, and respective contacts, e.g.47, on an opposing surface of the substrate 14. The die 18 is thenencapsulated within the molding material 24 at step 240. Balls areattached to the contacts 28 at step 250, and at step 260 die carriers 12within a carrier strip or matrix are singulated.

[0025] Referring now to FIG. 7, a semiconductor die package 100constructed in accordance with the invention can be used to package amemory circuit, such as a DRAM device 312, or any other electronicintegrated circuit, for use within a processor-based system 300. Theprocessor-based system 300 may be a computer system, a process controlsystem or any other system employing a processor and associated memory.The system 300 includes a central processing unit (CPU) 302, which maybe a microprocessor. The CPU 302 communicates with the DRAM device 312,which has memory cells 313, over a bus 316. The DRAM 312 package 100 isas described above with reference to FIGS. 4-6. The CPU 302 furthercommunicates with one or more I/O devices 308, 310 over the bus 316.Although illustrated as a single bus, the bus 316 may be a series ofbuses and bridges commonly used in a processor-based system. Furthercomponents of the system 300 may include a read only memory (ROM) device314 and peripheral devices such as a floppy disk drive 304, and CD-ROMdrive 306. The floppy disk drive 304 and CD-ROM drive 306 communicatewith the CPU 302 over the bus 316. As noted, any of the electronicelements of FIG. 6 which are packaged as an integrated circuit may alsoemploy the packaging structure and method of the invention, includingbut not limited to the central processing unit 302.

[0026] The invention provides a semiconductor chip with enhancedcompression resistant capabilities. The invention further provides amethod for fabricating such a semiconductor chip.

[0027] While the invention has been described in detail in connectionwith the preferred embodiments known at the time, it should be readilyunderstood that the invention is not limited to such disclosedembodiments. Rather, the invention can be modified to incorporate anynumber of variations, alterations, substitutions or equivalentarrangements not heretofore described, but which are commensurate withthe spirit and scope of the invention. Accordingly, the invention is notto be seen as limited by the foregoing description, but is only limitedby the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A semiconductor device packaging structure,comprising: a substrate containing a wiring pattern and a location formounting a die for connection with said wiring pattern; said substratecontaining at least one opening extending at least partially into saidsubstrate; and a material positioned within said opening, said materialhaving a greater resistance to compressive forces than said substrate.2. The semiconductor device packaging structure of claim 1, wherein saidopening is a hole.
 3. The semiconductor device packaging structure ofclaim 1, wherein said hole is a slot.
 4. The semiconductor devicepackaging structure of claim 1, further including a solder maskpositioned on a surface of said substrate, said solder mask exposingportions of said wiring pattern for allowing electrical connections tosaid wiring pattern.
 5. The semiconductor device packaging structure ofclaim 4, wherein said opening extends through said solder mask.
 6. Thesemiconductor device packaging structure of claim 1, wherein saidopening extends completely through said substrate.
 7. The semiconductordevice packaging structure of claim 6, wherein said opening hassidewalls lined with a conductive material.
 8. The semiconductor devicepackaging structure of claim 7, wherein said conductive materialcomprises copper.
 9. The semiconductor device packaging structure ofclaim 7, wherein said opening is a via.
 10. The semiconductor devicepackaging structure of claim 1, wherein said material comprises anepoxy.
 11. The semiconductor device packaging structrue of claim 10,wherein said epoxy contains particles.
 12. The semiconductor devicepackaging structrue of claim 11, wherein said particles comprise silica.13. The semiconductor device packaging structure of claim 1, furthercomprising a mold material encapsulating a portion of said structure.14. The semiconductor device packaging structure of claim 1, whereinsaid substrate comprises a glass weave resin.
 15. The semiconductordevice packaging structure of claim 1, wherein said substrate comprisesa tape.
 16. A packaged semiconductor die, comprising: a die; a substratemounting said die, said substrate comprising an interposer layer; aplurality of openings in said interposer layer; wiring supported by saidinterposer layer, said wiring connected to electrical terminals on saiddie; a material positioned within said plurality of openings, saidmaterial having a greater resistance to compressive forces than saidinterposer layer; and a molding material which secures said die to saidsubstrate.
 17. The packaged semiconductor die of claim 16, furthercomprising a first solder mask positioned on a first surface of saidinterposer layer.
 18. The packaged semiconductor die of claim 17,further comprising a second solder mask layer between said die and asecond surface of said interposer layer, wherein at least one of saidplurality of openings extends through at least one of said solder masklayers.
 19. The packaged semiconductor die of claim 18, wherein at leastone said plurality of openings extends through both said solder masklayers and said interposer layer.
 20. The packaged semiconductor die ofclaim 16, wherein at least one of said plurality of openings forms partof a conductive via which extends through said interposer layer.
 21. Thepackaged semiconductor die of claim 20, wherein said conductive viacomprises sidewalls lined with a conductive material.
 22. The packagedsemiconductor die of claim 21, wherein said conductive materialcomprises copper.
 23. The packaged semiconductor die of claim 16,wherein at least one of said plurality of openings extend partiallythrough said interposer layer.
 24. The packaged semiconductor die ofclaim 16, wherein at least one of said plurality of openings extendcompletely through said interposer layer.
 25. The packaged semiconductordie of claim 16, wherein at least one of said plurality of openings hasa circular cross-section.
 26. The packaged semiconductor die of claim16, wherein at least one of said plurality of openings comprises a slot.27. The packaged semiconductor die of claim 26, wherein said slot isL-shaped.
 28. The packaged semiconductor die of claim 16, wherein saidmaterial comprises an epoxy.
 29. The packaged semiconductor die of claim16, wherein said interposer layer comprises a glass weave resin.
 30. Thepackaged semiconductor die of claim 16, wherein said interposer layercomprises a tape.
 31. The packaged semiconductor die of claim 16,wherein said die comprises a memory device.
 32. A processor-basedsystem, comprising: a processing unit; and an integrated circuit devicecoupled to said processing unit, at least one of said processing unitand integrated circuit device comprising a packaged semiconductor die,said packaged semiconductor die comprising: a substrate containing awiring pattern and a location for mounting a die for connection withsaid wiring pattern, said substrate containing at least one openingextending at least partially into said substrate; a die mounted at saiddie location; and a material positioned within said opening, saidmaterial having a greater resistance to compressive forces than saidsubstrate.
 33. The system of claim 32, wherein said die contains saidprocessing unit.
 34. The system of claim 32, wherein said die containssaid integrated circuit device.
 35. The system of claim 34, wherein saidintegrated circuit device comprises a memory device.
 36. The system ofclaim 32, further including a solder mask positioned on a surface ofsaid substrate.
 37. The system of claim 36, wherein said opening extendsthrough said solder mask.
 38. The system of claim 32, wherein saidopening extends completely through said substrate.
 39. The system ofclaim 38, wherein said opening has sidewalls lined with a conductivematerial.
 40. The system of claim 39, wherein said conductive materialcomprises copper.
 41. The system of claim 32, wherein said materialcomprises an epoxy.
 42. The system of claim 41, wherein said epoxycontains particles.
 43. The system of claim 42, wherein said particlescomprise silica.
 44. The system of claim 32, further comprising a moldmaterial encapsulating a portion of said structure.
 45. A method ofpackaging a semiconductor die, comprising: (a) attaching a die to asemiconductor chip carrier, said carrier including a plurality ofopenings, at least one of said plurality of openings including acompression resistant material having a greater resistance tocompressive forces than said carrier; and (b) encapsulating said die andat least a portion of said carrier with a mold material.
 46. The methodof claim 45, further comprising electrically connecting said die to awiring pattern on said carrier.
 47. The method of claim 46, wherein saidwiring pattern comprises a printed wiring pattern.
 48. The method ofclaim 45, wherein said opening is a via, said compression resistantmaterial being surrounded by said conductive lining.
 49. The method ofclaim 48, wherein said via comtains a conductive lining on sidewalls ofthe via.
 50. The method of claim 45, wherein said opening comprises aslot.
 51. The method of claim 50, wherein said slot is an L-shaped slot.52. The method of claim 45, wherein said opening extends at leastpartially through said carrier.
 53. The method of claim 52, wherein saidopening extends through said carrier.